The PPC is the equivalent of the Pentium chip from intel in terms of performance and speed.
True, though most definitely not in terms of complexity - RISC architectures like the ARM and PPC presumably do not impose overly taxing demands on the overall resources within an FPGA, probably much less so than anything x86-related..
While the gate count ultimately speaks to the potential design complexity, you don't need to reproduce the hardware at a gate level.. you just need to be able to reproduce the correct results. I'm not sure how Hardware Description Languages (HDL's) and FPGA's hold up against Moore's law- but it seems to me that FPGA cores are really just hardware emulation layers.. so transistor count / performance may be way different.
Also, later Intel chips are not exclusively CISC.. there is a lot of RISC concepts swirled into the design as well. Like I said, if you can emulate it well enough.. why worry about the "gate level" details?
The PPC is the equivalent of the Pentium chip from intel in terms of performance and speed.
True, though most definitely not in terms of complexity - RISC architectures like the ARM and PPC presumably do not impose overly taxing demands on the overall resources within an FPGA, probably much less so than anything x86-related..
While the gate count ultimately speaks to the potential design complexity, you don't need to reproduce the hardware at a gate level.. you just need to be able to reproduce the correct results. I'm not sure how Hardware Description Languages (HDL's) and FPGA's hold up against Moore's law- but it seems to me that FPGA cores are really just hardware emulation layers.. so transistor count / performance may be way different.
Also, later Intel chips are not exclusively CISC.. there is a lot of RISC concepts swirled into the design as well. Like I said, if you can emulate it well enough.. why worry about the "gate level" details?